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| HANBit HSD16M32M4V Synchronous DRAM Module 64Mbyte ( 16M x 32-Bit ) 72-Pin SIMM based on 16Mx8, 4Banks, 4K Ref., 3.3V Part No. HSD16M32M4V GENERAL DESCRIPTION The HSD16M32M4V is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 4M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages mounted on a 72-pin, FR-4-printed circuit board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The HSD16M32M4V is a SIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES * Part Identification HSD16M32M4V-13/F13 :133MHz ( CL=3) HSD16M32M4V-12/F12: 125MHz (CL=3) HSD16M32M4V-10/F10: 100MHz (CL=2) HSD16M32M4V-10L/F10L: 100MHz HSD16M32M4V-66/F66: 66MHz (CL=2&3) F means Auto & Self refresh with Low-Power (3.3V) * Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * FR4-PCB design * The used device is KM48S16030AT * Pin assignment is compatible with - HSD8M32M4V - HSD32M32M4V PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN ASSIGNMENT SYMBOL Vss DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM0 Vcc NC A0 A1 A2 A3 A4 Vss DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ14 DQ15 DQM1 NC /WE /CAS Vcc /RAS /CS0 NC NC CLK0 CKE0 Vss DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM2 Vcc PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL A5 A6 A7 A8 A9 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM3 NC A10/AP A11 NC Vcc BA0 BA1 NC NC Vss 72-PIN SIMM TOP VIEW URL: www.hbe.co.kr REV 1.0 (August.2002) -1- HANBit Electronics Co.,Ltd. HANBit FUNCTIONAL BLOCK DIAGRAM DQ0-31 HSD16M32M4V CKE0 /CA S /RAS /CE1 CKE CAS RAS CE 1 WE A0-A11 CLK CLK0 U1 DQ0-7 DQM0 BA0DQM0 CKE CAS 15 RAS CE 1 WE A0-A11 CLK CLK0 U2 DQ8DQM1 DQM0 BA0- CKE CAS 23 RAS CE 1 WE A0-A11 CLK CLK0 U3 DQ16DQM2 DQM0 BA0- CKE CAS 31 RAS CE 1 WE A0-A11 CLK CLK0 U4 DQ24DQM3 DQM0 BA0- /WE A0 - A11 BA0-1 Vcc Vss Two 0.01uF Capacitor per each SDRAM URL: www.hbe.co.kr REV 1.0 (August.2002) -2- HANBit Electronics Co.,Ltd. HANBit PIN FUNCTION DESCRIPTION Pin CLK /CE Name System clock Chip enable Input Function HSD16M32M4V Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 BA1 /RAS ~ Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 31 VDD/VSS Data input/output Power supply/ground Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1V to 4.6V -1V to 4.6V 4W -55oC to 150oC Short Circuit Output Current IOS 50mA Notes : Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. URL: www.hbe.co.kr REV 1.0 (August.2002) -3- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23 C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Address(A0~A12, BA0~BA1) /RAS, /CAS, /WE CKE(CKE0) Clock (CLK0) /CE (/CE1) DQM (DQM0 ~ DQM3) DQ (DQ0 ~ DQ32) SYMBOL CADD C IN CCKE CCLK CCS CDQM COUT MIN 15 15 15 7.5 15 6.5 7 MAX 25 25 25 9 25 7.5 8.5 UNITS pF pF pF pF pF pF pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70 C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current ICC1 (One bank active) tRC tRC(min) IO = 0mA Precharge standby current in power-down mode ICC2PS ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= 4 mA 4 mA 48 440 0 440 0 44 440 mA 1 -A -8 -H -L -10 VERSION UNIT E NOT URL: www.hbe.co.kr REV 1.0 (August.2002) -4- HANBit Electronics Co.,Ltd. HANBit CKE VIH(min) ICC2N Precharge standby current in non power-down mode ICC2NS CS* VIH(min), tCC=10ns Input signals are changed one time during 20ns CKE VIH(min) CLK VIL(max), tCC= Input signals are stable ICC3P Active standby current in power-down mode ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), CS*VIH(min), tCC=10ns ICC3N Active standby current in non power-down mode (One bank active) ICC3NS Input signals are changed one time during 20ns CKEVIH(min) CLK VIL(max), tCC= Input signals are stable IO = 0 mA Operating current ICC4 (Burst mode) 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC tRC(min) 88 880 0 6 3.2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 840 0 Page burst 60 580 500 80 120 20 28 80 HSD16M32M4V mA mA 20 mA 500 500 mA 1 840 840 mA mA mA 2 G F Self refresh current ICC6 CKE 0.2V AC OPERATING TEST CONDITIONS (vcc = 3.3V 0.3V, TA = 0 to 70 C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V URL: www.hbe.co.kr REV 1.0 (August.2002) -5- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V +3.3V Vtt=1.4V 1200 DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit DOUT Z0=50 50pF 50 OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data CAS latency=2 1 SYMBOL -A tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max) tRC(min) UNIT -8 16 20 20 48 -H 20 20 20 50 100 65 68 70 2 2 CLK + 20 ns 1 1 1 2 ea 70 80 -L 20 20 20 50 -10 20 24 24 50 ns ns ns ns ns ns CLK CLK CLK CLK 15 20 20 45 NOTE 1 1 1 1 1 2.5 5 2 2 3 4 tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) URL: www.hbe.co.kr REV 1.0 (August.2002) -6- HANBit Electronics Co.,Ltd. HANBit AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -A SYM PARAMETER BOL X CLK cycle time CAS 7.5 latency=3 tCC CAS latency=2 CLK to valid output delay CAS 5.4 latency=3 tSAC CAS latency=2 Output data hold time CAS 2.7 latency=3 tOH CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS 5.4 latency=3 tSHZ CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. 7 6 6 6 6 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 3 3 2 1 1 3 3 2 1 1 3 3 2 1 1 3 3 3 3 3 7 6 6 6 6 12 1000 0 10 8 10 1000 100 1000 10 MIN MAX MIN MAX MIN MA MIN MAX -8 -H -L HSD16M32M4V -10 NOT MIN MAX UNIT E 10 1000 13 ns 1 7 ns 7 1,2 3 ns 3 3.5 3.5 2.5 1.5 1 7 ns ns ns ns ns ns 3 3 3 3 3 2 2 7 ns SIMPLIFIED TRUTH TABLE COMMAND Register Mode register set Auto refresh Refresh Self refres h Entry Exit CKE n-1 H H L H CKE n X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1 A10/ AP OP code X X Row address HANBit Electronics Co.,Ltd. A11 A9~A0 NOTE 1,2 3 3 3 3 Bank active & row addr. URL: www.hbe.co.kr REV 1.0 (August.2002) -7- HANBit Auto disable Auto disable Auto disable Auto disable Burst Stop Precharg e Bank selection All banks Entry Exit Entry Exit H H H L H L H H X H L X X L H L H L L H L X H L H L L L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X V X precharge precharge H X L H L L X V precharge precharge H X L H L H X V HSD16M32M4V Read & column address L H Column Address (A0 ~ A9) Column 4 4,5 Write & column address L Address (A0 ~ A9) 4 H X L H X X 4,5 6 Clock suspend or active power down Precharge down mode DQM power X X V X X X 7 No operation command (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) TIMING DIAGRAMS Please refer to timing diagram chart (II) URL: www.hbe.co.kr REV 1.0 (August.2002) -8- HANBit Electronics Co.,Ltd. HANBit PACKAGING INFORMATION HSD16M32M4V Unit : mm 107.95 20 17.8 0.2 3.38 3.2 t 10.16 6.35 2.03 44.45 1.27 1.00 95.25 6.35 6.35 2.54 0.25 MAX MIN 1.270.08 Gold: 1.040.10 1.27 Solder: 0.9140.10 (Solder & Gold Plating) URL: www.hbe.co.kr REV 1.0 (August.2002) -9- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V ORDERING INFORMATION Part Number Density Org. Package 72 Pin SIMM 72 Pin SIMM 72 Pin SMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM Ref. Vcc Feature MAX.frq 133MHz (CL=3) HSD16M32M4V-13 HSD16M32M4V-F13 HSD16M32M4V-12 HSD16M32M4V-F12 HSD16M32M4V-10 HSD16M32M4V-F10 HSD16M32M4V-10L HSD16M32M4V-F10L 64MByte 64MByte 64MByte 64MByte 64MByte 64MByte 64MByte 64MByte 16Mx 32 16Mx 32 16Mx 32 16Mx 32 16Mx 32 16Mx 32 16Mx 32 16Mx 32 4K 4K 4K 4K 4K 4K 4K 4K 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Low Power Low Power Low Power Low Power 133MHz (CL=3) 125MHz (CL=3) 125MHz (CL=3) 100MHz (CL=2) 100MHz (CL=2) 100MHz 100MHz URL: www.hbe.co.kr REV 1.0 (August.2002) - 10 - HANBit Electronics Co.,Ltd. |
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